Logic Synthesis Strategy Oriented to Low Power Optimization

The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means BDD. A new form the SWitch activity BDD diagram (SWBDD) is proposed, which enables function decomposition to minimize switching circuits. essence proposed idea lies proper ordering variables and cutting diagram, ensuring minimization combination circuit. This contains results experiments confirming effectiveness developed concept decomposition. They were performed popular benchmarks using academic commercial systems.